منابع مشابه
PHYSICAL DESIGN METHODOLOGIES FOR LOW POWER AND RELIABLE 3D ICs
Title of dissertation: PHYSICAL DESIGN METHODOLOGIES FOR LOW POWER AND RELIABLE 3D ICs Tiantao Lu, Doctor of Philosophy, 2016 Dissertation directed by: Professor Ankur Srivastava Department of Electrical Engineering As the semiconductor industry struggles to maintain its momentum down the path following the Moore’s Law, three dimensional integrated circuit (3D IC) technology has emerged as a pr...
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Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis stage. However, previous work may suffer from a large circuit area overhead on the clock control logic. In this paper, we present an I...
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With the progress of VLSI technology, delay buffer plays an important role affecting the circuit design and performance. This paper presents the design of low power buffer using clock gating and gated driver tree. Since delay buffers are accessed sequentially, it adopts a gated clock ring counter addressing scheme. The ring counter employs double edge triggered (DET) flip flops instead of tradi...
متن کاملFPGA Clock Management for Low Power
Clock management circuits are relatively new FPGA architectural blocks that are critical to solving clock distribution problems associated with high-speed, high-density designs. We outline the use of three FPGA clock managers in a variety of applications, and consider their application to low-power systems which adjust clock rates based on the amount of computation needed. Dynamic clock managem...
متن کاملA low power sinusoidal clock
This paper describes a low power clock distribution that utilizes sinusoidal clock waveforms and proposes registers that are able to cope with the overlapping clock edges. We can report power savings of 30% to 70% compared with conventional clocking schemes while maintaining traditional static CMOS design styles and logic levels.
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ژورنال
عنوان ژورنال: ACM Transactions on Design Automation of Electronic Systems
سال: 2017
ISSN: 1084-4309,1557-7309
DOI: 10.1145/3019610